The present invention relates generally to barrier layers in semiconductor capacitors, and in particular to development of semiconductor capacitor structures having at least one metal oxynitride barrier layer, and apparatus making use of such capacitor structures.
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor typically includes two conductive electrodes separated by a dielectric layer. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of a digit line pair through an access transistor.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells are shared with their associated digit lines, and data is sensed and latched to the digit line pairs.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is generally a function of electrode area. Additionally, there is a continuing goal to further decrease memory cell area.
A principal method of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom electrode of the capacitor. Such container structures may have shapes differing from a substantially cylindrical form, such as an oval or other three-dimensional container. The container structures may further incorporate fins.
Another method of increasing cell capacitance is through the use of high dielectric constant material in the dielectric layer of the capacitor. In order to achieve the charge storage efficiency generally needed in 256 megabit(Mb) memories and above, materials having a high dielectric constant, and typically dielectric constants greater than 50, can be used in the dielectric layer between the bottom electrode and the top electrode of the capacitor. The dielectric constant is a characteristic value of a material and is generally defined as the ratio of the amount of charge that can be stored in the material when it is interposed between two electrodes relative to the charge that can be stored when the two electrodes are separated by a vacuum.
Unfortunately, high dielectric constant materials are often incompatible with existing processes. One cause of such incompatibility can be the oxygen-containing ambient often present during the deposition of high dielectric constant materials or during subsequent annealing processes. Other causes of incompatibility may be adverse chemical reactions or oxygen diffusion between t he material of the dielectric layer and the material of an adjoining electrode due to direct contact.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative capacitor structures and methods of producing same.
Embodiments of the invention include capacitors having a metal oxynitride barrier layer interposed between an electrode and a dielectric layer, and methods of their formation. The metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. The metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric layer.
For one embodiment, the invention includes a capacitor. The capacitor includes a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor further includes at least one metal oxynitride barrier layer. Each metal oxynitride barrier layer is interposed between the dielectric layer and either the bottom electrode or the top electrode.
For another embodiment, the invention includes a capacitor. The capacitor includes a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor further includes a metal oxynitride barrier layer interposed between the dielectric layer and the bottom electrode.
The capacitor still further includes a metal oxynitride barrier layer interposed between the dielectric layer and the top electrode.
For a further embodiment, the invention includes a capacitor. The capacitor includes a bottom electrode, a top electrode and a metal oxide dielectric layer interposed between the bottom electrode and the top electrode. The capacitor further includes at least one metal oxynitride barrier layer. Each metal oxynitride barrier layer is interposed between the dielectric layer and either the bottom electrode or the top electrode. For one embodiment, the bottom electrode, the top electrode or both electrodes contain metal nitride. For another embodiment, the dielectric layer contains at least one metal oxide dielectric material selected from the group consisting of BazSr(1xe2x88x92z)TiO3[BST; where 0 less than z less than 1], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3[PZT], (Pb,La)(Zr,Ti)O3[PLZT], (Pb,La)TiO3[PLT], Ta2O5, KNO3, Al2O3 and LiNbO3. For yet another embodiment, the metal oxynitride barrier layer contains a metal oxynitride having a composition of the form MOxNy. The metal component M may be a refractory metal. The refractory metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are included in this definition. For a further embodiment, the metal component M may be of the platinum metals group, such as iridium (Ir), osmium (Os), palladium (Pd), platinum (Pt), rhodium (Rh) or ruthenium (Ru), or the noble metals group, such as gold (Au), iridium, osmium, palladium, platinum, rhenium (Re), rhodium or ruthenium. For another embodiment, the metal component M is selected from the group consisting of chromium, cobalt, hafnium, iridium, molybdenum, niobium, osmium, rhenium, rhodium, ruthenium, tantalum, titanium, tungsten, vanadium and zirconium.
For one embodiment, the invention includes a capacitor. The capacitor includes a bottom electrode, a top electrode and a metal oxide dielectric layer interposed between the bottom electrode and the top electrode. The capacitor further includes a tungsten oxynitride barrier layer interposed between the dielectric layer and the bottom electrode. The capacitor still further includes a tungsten oxynitride barrier layer interposed between the dielectric layer and the top electrode. For another embodiment, the bottom and top electrodes contain tungsten nitride. For a further embodiment, the dielectric layer contains tantalum oxide.
For another embodiment, the invention includes a method of forming a capacitor. The method includes forming a bottom electrode layer, forming a first metal oxynitride barrier layer overlying the bottom electrode layer, forming a dielectric layer overlying the first metal oxynitride barrier layer, forming a second metal oxynitride barrier layer overlying the dielectric layer, and forming a top electrode layer overlying the second metal oxynitride barrier layer.
For still another embodiment, the invention includes a method of forming a capacitor. The method includes forming a bottom electrode layer, forming a metal oxynitride barrier layer overlying the bottom electrode layer, forming a dielectric layer overlying the metal oxynitride barrier layer, and forming a top electrode layer overlying the dielectric layer.
For yet another embodiment, the invention includes a method of forming a capacitor. The method includes forming a bottom electrode layer, forming a dielectric layer overlying the bottom electrode layer, forming a metal oxynitride barrier layer overlying the dielectric layer, and forming a top electrode layer overlying the metal oxynitride barrier layer.
Further embodiments of the invention include semiconductor structures and methods of varying scope, as well as apparatus, devices, modules and systems making use of such semiconductor structures and methods.